# Computer Organization and Architecture Assignment Help (Computer Architecture Homework Help)

1. Convert the following machine code instruction to assembly language

0xD3400D4B

1. STUR X13, [X12 #16]
2. AND X15, X14, X13
3. SUBS X13, X14, X15
5. LSR X11, X10, #3
6. LDUR X11, [X10, #8]
7. CBNZ X11, #68
8. CBZ X9, #72
9. B #96
10. BL #36
11. For the purpose of this problem, assume that the cbz instruction has a CPI of 7 but all other instructions in our ARM subset have a CPI of 5. A program consisting of 2,000,000 instruction is executed running at a 1 GHz clock rate. The program uses the following mix of instructions. 40% R-type, 10% Idur, 10% stur, 40% cbz.
1. Convert the following machine code instruction to assembly language

0xD3400D4B

STUR X13, [X12 #16]

AND X15, X14, X13

SUBS X13, X14, X15

LSR X11, X10, #3

LDUR X11, [X10, #8]

CBNZ X11, #68

CBZ X9, #72

B #96

BL #36

Q. For the purpose of this problem, assume that the cbz instruction has a CPI of 7 but all other instructions in our ARM subset have a CPI of 5. A program consisting of 2,000,000 instruction is executed running at a 1 GHz clock rate. The program uses the following mix of instructions. 40% R-type, 10% Idur, 10% stur, 40% cbz.

Q. What is the average CPI? (answer)

Q. What speedup would result if the cbz were improved to CPI = 5? (answer)

Q. Fill in the blanks with ARM assembly code corresponding to the given comments. USE ALL CAPS FOR MNEMONICS ANDLETTERS IN REGISTER NAMES FOR AUTOGRADING. Don’t include a semi-colon at the end of your statements.

Variables a,b,c and d are passed in as arguments, in that order.

(answer) #subtract a from b and place in register X13

Else:

Exit:Describe the code in the previous question does.

Q. We are multiplying two eight bit numbers.

Q. How may bits is the product? (ANSWER)

Q. Out multiplier is 2710 and out multiplicand is 510

Q. Given are the first three iterations of the flow chart above. Fill in step a and step b for iteration 4

0000000000011011

Iteration Step a                     step b

1. 0000010100011011 ->        0000001010001101
2. 0000011110001101 ->        0000001111000110
3. 0000001111000110 ->        0000000111100011

Q. What is the 32 bit IEEE 754 floating point format representation for -100? Q. Give your answer in hexadecimal. Show your work

Q. How many control lines are needed by a decoder to choose one of 47 outputs to activate?

Q. For instruction

STUR x9, [x10,0]

What value is contained in register x10?

1. The value to be transferred from memory to register
2. The value to be transferred from register to memory
3. The address in memory of the value that is to be transferred to a register
4. The address in memory that a value in a register is to be transferred to

Q. Show work for partial credit,

a) Computer A has a clock speed of 5 GHz, it runs a program with 15,000 instructions.. 10% of the instructions take 5 clock cycles, 60% of the instructions take 4 clock cycles and 30% of the instructions take 3 clock cycles. What is the execution time of the program?

b) The program was compiled on Computer B that has a clock speed of 4GHz. It resulted in 10000 instructions, with the same distribution of 10% of the instructions taking 5 clock cycles, 60% of the instructions taking 4 clock cycles and 30% of the instructions taking 3 clock cycles. What is the speedup of Computer B over Computer A.

Q. Convert the following number to 16 bit two’s complement binary then to hexadecimal.

-45

Show your work. No credit if work is not shown.

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